Implementation of a low power 16-bit radix-4 pipelined SRT divider using a modified Split-Path Data Driven Dynamic Logic (SPD3L) structure

In this paper a 16-bit radix-4 pipelined divider implemented in a modified version of SPD3L family structure (SPCD3L: Split-Path Clock-Data driven Dynamic Logic) is presented. Through the modification, the clock signal is also used to pre-charge some critical parts of the circuit. Performance of the circuit is evaluated at different simulation corners. The results show that, compared with Domino structure, the proposed circuit has lower power consumption and higher speed. Latency of the divider is equal to 10 half clock cycles. The design is simulated using HSPICE in a 1.8-V TSMC_180 nm CMOS process.