A current mode active pixel with high sensitivity pinned PD in standard CMOS process for smart image sensors

In this paper we present a current mode structure for Active Pixel Sensor (APS) which is an essential part in fast Smart CMOS Image Sensors (SCIS). Using two diodes (N+/P-Well and P-Well/Deep-N-Well) in parallel like a Pinned Photo-Diode (PPD) improves sensing of optical signal and leads to higher sensitivity than a conventional Photo-Diode (PD). Also integrated signal amplification inside the collection area of the pixel increases the sensitivity of the device due to the amplification in the pixel. The proposed structure with regards to using Deep-N-Well/P-Substrate junction as a guard ring, suppresses the pixel Cross-Talk (CTK) highly. In pixel Delta Reset Sampling (DRS) architecture helps to make feasible on-chip parallel processing. A post layout simulation for test structure of the proposed current mode APS has been considered by standard 0.18 µm RF-CMOS technology of TSMC with a 10 µm×10 µm PD size. Fill factor of each pixel is 24%.