Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models

In this paper we present the results of the implementation of a nanoscale double-gate (DG) MOSFET compact model, which includes hydrodynamic transport model, in Verilog-A in order to carry out circuit simulation. The model in Verilog-A is used with the SMASH circuit simulator for the analysis of the DC and transient behavior electrical CMOS circuits. Template devices representative for a downscaled symmetric double-gate MOSFET was used to validate the models for n-channel and p-channel. A CMOS inverter and a ring oscillator have been analyzed. Comparison of its performance between the drift-diffusion (DD) and hydrodynamic transport model within the practical range of bias voltages has been highlighted.