Adaptive successive approximation ADC for biomedical acquisition system

This work proposes a low-power adaptive successive approximation ADC that operates in 12-bit and 8-bit resolution for data acquisition in biomedical system. A fully differential architecture and an energy-efficient switching scheme are employed. The modified switching operation allows the output voltage of the DAC capacitor array to approach the common mode voltage in order to reduce the offset voltage variation of the comparator. A test chip is implemented using a 0.18-µm CMOS process. The core area is 904×650 μm2 The measurement results show that performance integrity and power efficiency are both significantly achieved in 12-bit resolution only. After the test using 1.8-V supply voltage, the SNDR is 65.59 dB and ENOB is 10.62 bits. Using 200 kS/s sampling rate, the ADC core consumption is 40.24 μW and 18.63 μW, for 12-bit and 8-bit case, respectively.