A class of fault-tolerant systolic arrays for matrix multiplication

This paper presents a proposal for a systematic approach for designing one class of fault-tolerant systolic arrays with orthogonal interconnects and unidirectional data flow (OUSA) for multiplication of rectangular matrices. The method employs space-time redundancy to achieve fault-tolerance. It consists of four steps. In the first step the inner computation space of the basic systolic algorithm for matrix multiplication is expanded. In the second step we derive a matrix multiplication algorithm which enables us to obtain OUSAs with data pipeline period λ=3λ=3. During the third step redundancy is introduced by deriving three equivalent algorithms with disjoint index spaces. In the last step the obtained algorithm is mapped into a processor-time domain. In this way we have obtained four different OUSAs. For the given matrix dimensions, two out of four arrays have an optimal number of processing elements (PEs) and minimal execution time. For the square case, all arrays have an optimal number of PEs, Ω=n(n+2)Ω=n(n+2), and total execution time of Ttot=6nTtot=6n. All of them can tolerate single transient errors and the majority of multiple error patterns with high probability. In addition, two arrays can tolerate permanent faults as well. The obtained arrays are suitable for implementation in VLSI technology. Compared to a hexagonal array of the same dimensions, the number of I/O pins is reduced by approximately 30%.