کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
1141736 1489500 2014 7 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Easy and difficult exact covering problems arising in VLSI power reduction by clock gating
موضوعات مرتبط
مهندسی و علوم پایه ریاضیات کنترل و بهینه سازی
پیش نمایش صفحه اول مقاله
Easy and difficult exact covering problems arising in VLSI power reduction by clock gating
چکیده انگلیسی

Several graph matching and exact covering problems arising in VLSI low-power design optimization by clock gating are presented. To maximize the power savings, clock gating requires optimal grouping of Flip-Flops (FFs), which depends on FFs’ data toggling correlations and probabilities. These naturally lead to optimal matching and exact covering problems. We present three problems arising by different clock-gating techniques. In a method called data-driven clock-gating, the corresponding covering problem is intractable but can practically be solved by appropriate heuristics. In another method called multi-bit flip-flops, the covering problem is easily solvable in a closed-form, required only sorting. We finally present the covering problem arising in a new method called look-ahead clock-gating, for which the question of whether the exact covering problem is easy or difficult is left open.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Discrete Optimization - Volume 14, November 2014, Pages 104–110
نویسندگان
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