Improving the performance of amorphous and crystalline silicon heterojunction solar cells by monitoring surface passivation

The influence of thermal annealing on the crystalline silicon surface passivating properties of selected amorphous silicon containing layer stacks (including intrinsic and doped films), as well as the correlation with silicon heterojunction solar cell performance has been investigated. All samples have been isochronally annealed for 1 h in an N2 ambient at temperatures between 150 °C and 300 °C in incremental steps of 15 °C. For intrinsic films and intrinsic/n-type stacks, an improvement in passivation quality is observed up to 255 °C and 270 °C, respectively, and a deterioration at higher temperatures. For intrinsic/n-type a-Si:H layer stacks, a maximum minority carrier lifetime of 13.3 ms at an injection level of 1015 cm− 3 has been measured. In contrast, for intrinsic/p-type a-Si:H layer stacks, a deterioration in passivation is observed upon annealing over the whole temperature range. Comparing the lifetime values and trends for the different layer stacks to the performance of the corresponding cells, it is inferred that the intrinsic/p-layer stack is limiting device performance. Furthermore, thermal annealing of p-type layers should be avoided entirely. We therefore propose an adapted processing sequence, leading to a substantial improvement in efficiency to 16.7%, well above the efficiency of 15.8% obtained with the ‘standard’ processing sequence.

► Excellent crystalline silicon surface passivation obtained.
► Modified processing order for silicon heterojunction solar cells proposed.
► An efficiency of 16.7% is obtained on flat c-Si.
► Relative improvement of 6% versus standard order obtained.