Analysis of the energy distribution of interface traps related to tunnel oxide degradation using charge pumping techniques for 3D NAND flash applications

• Dit is directly investigated from bulk-type and TFT-type CTF memory.
• Charge pumping technique was employed to analyze the Dit information.
• To apply the CP technique to monitor the reliability of the 3D NAND flash.

The energy distribution and density of interface traps (Dit) are directly investigated from bulk-type and thin-film transistor (TFT)-type charge trap flash memory cells with tunnel oxide degradation, under program/erase (P/E) cycling using a charge pumping (CP) technique, in view of application in a 3-demension stackable NAND flash memory cell. After P/E cycling in bulk-type devices, the interface trap density gradually increased from 1.55 × 1012 cm−2 eV−1 to 3.66 × 1013 cm−2 eV−1 due to tunnel oxide damage, which was consistent with the subthreshold swing and transconductance degradation after P/E cycling. Its distribution moved toward shallow energy levels with increasing cycling numbers, which coincided with the decay rate degradation with short-term retention time. The tendency extracted with the CP technique for Dit of the TFT-type cells was similar to those of bulk-type cells.

The degradation tendency extracted by CP technique was almost the same in both the bulk-type and TFT-type cells.Figure optionsDownload as PowerPoint slide