Selective epitaxial growth of SiGe for strained Si transistors

A selective SiGe epitaxial growth for strained CMOS Si technology was developed for 65 nm logic technology generation that integrates with Ni silicidation. A 36% device performance improvement for PMOS devices was achieved using this technology. Key process parameters for this technology such as Si recess etch, epitaxial surface preparation, SiGe growth and Ni silicidation are discussed. Experimental results for these process parameters are also presented.