Photoluminescence and TEM evaluations of defects generated during SiGe-on-insulator virtual substrate fabrication: Temperature ramping process

Crystal qualities were evaluated by photoluminescence (PL) and transmission electron microscopy (TEM) for cap-Si/SiGe/Si-on-insulater (SOI) structure, which is the typical structure for SiGe-on-insulator virtual substrate fabrication using the Ge condensation by dry oxidation. The thicknesses of cap-Si, SOI and BOX layers are 10, 70, and 140 nm, respectively. We have three kinds of wafers with SiGe thicknesses of 74, 154 and 234 nm. All of the wafers were heated from 200 °C to a target temperature (Tt) in the range of 820–1200 °C with a ramping rate of 5 °C/min, and maintained at Tt for 10 min. The air in the furnace was a mixture of O2 and N2. The PL measurements were carried out using a 325 nm UV line of a continuous-wave HeCd laser. Free exciton peaks were clearly observed for the as-grown wafers and decreased with an increase in the annealing temperature. For the selected wafers, cross-sectional and plan-view TEM measurements show clear generation and variation of dislocations at the interface of SiGe/SOI according to the Tt. Defect-related PL signals were observed at around 0.82, 0.88, 0.95 and 1.0 eV, which also varied according to the Tt and the SiGe thickness. They were identified to dislocation-related and stacking-fault-related defects by TEM.