Numerical simulation of bias and photo stress on indium–gallium–zinc-oxide thin film transistors

• Numerical simulation is used to explain the threshold voltage shift of a-IGZO TFTs.
• Tail, deep and interface states cause a shift in the threshold voltage.
• A negative shift is observed if the defects are donor-like.
• A positive shift is observed if the defects are acceptor-like.
• Discrete interface levels induce a hump in the transfer characteristics.

Thin Film Transistors based on amorphous Indium–Gallium–Zinc-Oxide (a-IGZO TFT) are receiving a great deal of attention for their numerous applications as alternatives for amorphous and poly-crystalline Silicon based TFTs. A major concern about a-IGZO TFTs is that they suffer from instabilities when subjected to different types of stress (bias, light, etc …). Stress is believed to create defects of different kinds in different regions of the device. The instability manifests as a shift in the threshold voltage or a hump in the transfer characteristics of the transistor. In addition, there is still a great deal of confusion about the relation between defects and the instability induced by stress. The main purpose of this study is to elucidate the relation between the threshold voltage shift (instability) and the defects created by stress. For this purpose a detailed numerical simulation was carried out to investigate the relation between the different types of defects created by stress and the induced instability in a-IGZO TFT. It was found that tail, deep and interface states cause a shift in threshold voltage. Negative and positive shifts are observed if the defects are donor-like and acceptor-like defects, respectively. On the other hand, a hump in the transfer characteristics is induced if discrete interface levels are dominant.