Temperature dependent current–voltage characteristics of the Cd/CdO/n–Si/Au–Sb structure

In this study, this is the first time, it has been employed Successive Ionic Layer Adsorption and Reaction (SILAR) method in order to prepare Cd/CdO/n–Si/Au–Sb sandwich structure. The sample temperature effect on the current–voltage (I–V) characteristics of Cd/CdO/n–Si/Au–Sb structure has been investigated in a wide temperature range by steps of 20 K. The parameters such as barrier height, ideality factor and series resistance of this structure have been calculated from the forward bias I–V characteristics as a function of sample temperature. With a decreasing temperature, a decreasing in the apparent barrier height (Φb0), an increasing in the ideality factor (n) and a nonlinearity in the activation energy plot have been seen. The experimental values of barrier height and ideality factor for this device have been calculated as 0.871 eV and 1.787 at 300 K and 0.436 eV and 2.221 at 80 K, respectively. These abnormal behaviors can be explain by the barrier inhomogeneities at the metal–semiconductor (M–S) interface. From the temperature dependent I–V   characteristics of the Cd/CdO/n–Si/Au–Sb sandwich structure, Φ¯b0 and A∗ are calculated as 0.790 and 1.160 eV, and 153.90 and 188.42 A/cm2 K2, respectively, by using ln(I0/T2)-q2σs2/2k2T2 vs. 1/T plot for the two temperature regions. Deviation of experimental values of A∗ from known value for n–Si has been attributed to the spatial inhomogeneous barrier heights and potential fluctuations at the interface that consist of low and high barrier areas.