Thin film embedded memory solutions

CMOS evolution at Moore’s law speed modulated by market demand is facing extrinsic and intrinsic limitations. Main extrinsic drawback is process variability affecting yield production. Solutions to address this point are focused on design and integration at dice level. Intrinsic limitations are usually summarized through the term Short Channel Effects, SCE. To overcome parasitic SCE, device engineers consider building aggressively shrink CMOS transistors on thin silicon film. These devices, allow a better electrostatic potential control.New memory cell architecture can be evaluated on thin film technologies following CMOS evolution. Recent literature reports many efforts to utilize floating body effect [1] and [2] to enable volatile and non volatile memories. In this study we present how one transistor built on thin film can be considered for volatile and non volatile memory applications.Memory effects are electrically evaluated on thin Buried Oxide, BOx, Fully Depleted SOI, FDSOI, devices of sub 75 nm gate length.