Modeling semiconductor testing job scheduling and dynamic testing machine configuration

The overall flow of the final test of integrated circuits can be represented by the job shop model with limited simultaneous multiple resources in which various product mixes, jobs recirculation, uncertain arrival of jobs, and unstable processing times complicate the problem. Rather than relying on domain experts, this study aims to develop a hybrid approach including a mathematical programming model to optimize the testing job scheduling and an algorithm to specify the machine configuration of each job and allocate specific resources. Furthermore, a genetic algorithm is also developed to solve the problem in a short time for implementation. The results of detailed scheduling can be graphically represented as timetables of testing resources in Gantt charts. The empirical results demonstrated viability of the proposed approach.