High-level design space exploration of locally linear neuro-fuzzy models for embedded systems

Recently, artificial neural networks and neuro-fuzzy systems are being introduced in embedded systems due to often-used solution for classification and nonlinear system identification. In this paper, we present a parametric neuro-fuzzy hardware and a framework for exploring design space for an efficient hardware realization of neuro-fuzzy models for embedded systems. The proposed hardware can be used as a stand-alone core or be coupled with a central processing unit for the purpose of online training. We also present a framework to explore the design space for optimal design parameters (hardware core parameters) so that an efficient neuro-fuzzy hardware in terms of area, power consumption, and performance (delay) can be selected. It examines whole design space to find Pareto efficient hardware without increasing time-to-market and non-recurring engineering cost with the aid of high-level design space exploration. Also, the performance of the proposed hardware is compared against a soft core embedded processor named NIOS II/s. The results obtained show that the selected core is able to perform actions faster than NIOS II while it dissipates less power. Moreover, the proposed framework is put into action through three different scenarios to show off the capabilities of framework for generating Pareto optimal points upon different application demands.