An efficient hardware implementation for deblocking filter of AVS decoder

In this paper, an optimized hardware implementation for deblocking filter of AVS decoder was proposed according to the arithmetic in AVS audio video coding standard. In order to reduce the bandwidth requirement of SDRAM, internal RAM is used to cache reference data for deblocking filter in the hardware design. Meanwhile, the storage structure of reference data is reasonably arranged for accelerating filtering process. Based on the proposed data structure, both the SDRAM data writing operation and the macroblock filtering operation can be done at the same time. The design is implemented on an Altera Stratix II FPGA, the synthesis and simulation results indicated that the hardware cost was low, and the design can meet the demand of the real-time video decoding.