Design and implementation of Software Defined Hardware Counters for SDN

In Software-Defined Networking (SDN), central controllers can obtain global views of dynamic network statistics to manage their networks. In order to support SDN controllers to obtain global information of the networks, the data planes need to maintain a large number of counters, which are typically implemented in hardware such as ASIC. However, implementation of these counters in hardware faces critical challenges: high memory consumption, control inflexibility, and low statistical accuracy. In this paper, we present the concept of Software Defined Hardware Counters (SDHC) for SDN, which offloads the management of counter updating to software and still maintains practical execution efficiency in hardware. Therefore, SDHC can allocate counter memory on demand to enhance counter utilization, which greatly reduces on-chip memory consumption. It is able to allow controllers to flexibly control the counters through south-bound interface. Besides, with novel statistics feedback mechanisms, SDHC supports high-accuracy and active statistical requirement applications. Through a prototype implementation and performance evaluation based on FPGA and general processor, we reveal that the proposed SDHC is able to achieve high processing performance and high statistical accuracy, which incurs negligible updating delay to the switches.

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