Field programmable gate array implementation of spectrum allocation technique for cognitive radio networks

• To maximize the network utilization, spectrum allocation technique fairly allocates the channels to secondary users.
• SA problem is solved by Differential Evolution algorithm and compared the performance with PSO and FA.
• DE improved the quality of solution and time complexity by 29.9%, 242.32% and 19.04%, 46.3% compared to PSO and FA.
• We propose FPGA based coprocessor for DE-SA IP and interfaced to PowerPC.
• The coprocessor accelerates SA task by 76.79–105x and 5.19–6.91x compared to float and fixed DE-SA software.

Cognitive radio is an emerging technology in wireless communications for dynamically accessing under-utilized spectrum resources. In order to maximize the network utilization, vacant channels are assigned to cognitive users without interference to primary users. This is performed in the spectrum allocation (SA) module of the cognitive radio cycle. Spectrum allocation is a NP hard problem, thus the algorithmic time complexity increases with the cognitive radio network parameters. This paper addresses this by solving the SA problem using Differential Evolution (DE) algorithm and compared its quality of solution and time complexity with Particle Swarm Optimization (PSO) and Firefly algorithms. In addition to this, an Intellectual Property (IP) of DE based SA algorithm is developed and it is interfaced with PowerPC440 processor of Xilinx Virtex-5 FPGA via Auxiliary Processor Unit (APU) to accelerate the execution speed of spectrum allocation task. The acceleration of this coprocessor is compared with the equivalent floating and fixed point arithmetic implementation of the algorithm in the PowerPC440 processor. The simulation results show that the DE algorithm improves quality of solution and time complexity by 29.9% and 242.32%, 19.04% and 46.3% compared to PSO and Firefly algorithms. Furthermore, the implementation results show that the coprocessor accelerates the SA task by 76.79–105× and 5.19–6.91× compared to floating and fixed point implementation of the algorithm in PowerPC processor. It is also observed that the power consumption of the coprocessor is 26.5 mW.

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