Novel low-cost and fault-tolerant reversible logic adders

• A new low-cost gate is proposed with the quantum cost of 10 to be used as a parity preserving full adder with the minimum hardware complexity so far.
• New fault-tolerant reversible CLA, CSK and BCD adders are proposed with better design criteria.
• CMOS transistor-based implementation of the proposed designs is investigated.
• A new more precise delay computation is presented as an important criterion to be utilized in the comparisons.

In recent years, reversible logic circuits have received considerable attention due to their diverse applications in various fields. As the computing systems are susceptible to different environmental effects which can impact their intended operations, having the fault-tolerance capability is of great importance. In this paper, at first, a novel reversible gate is presented to achieve a parity preserving full adder which serves as the main building block of different adders. Further on, by using the proposed full adder and new arrangements of other reversible gates, some new low-cost fault-tolerant adders including binary coded decimal, carry skip and carry look-ahead architectures are presented. The new adders are highly efficient in the quantum cost, total logical calculation and transistor count compared to the existing designs. In addition, regarding other factors including the number of gates, garbage outputs and maximum delay, they are the best or among the favorite parity preserving reversible adders.