Accelerating image boundary detection by hardware parallelism

• A study to accelerate the boundary detection algorithm on FPGAs by exploiting different parallelisms was presented.
• The parallel Pb detector, with the working frequency of 200 MHz, takes 6.3 ms to process an image of 321 × 481.
• This paper provides a foundation for other gradient-based boundary detection algorithms to be accelerated by hardware.
• This paper demonstrates a way to improve the real-time performance of high-quality image boundary detection systems.

Image boundary can provide useful information for high-level tasks in computer vision applications. However, high-quality image boundary detection algorithms are computationally intensive, which limits their applicability in real-world applications. In this paper, a study on accelerating algorithms of image boundary detection by hardware parallelism is presented. The Pb (Probability boundary) algorithm, as one representative high-quality algorithm of gradient-based boundary detection, is selected. Firstly, different types of parallelisms existing in Pb are analyzed. Then, suitable hardware structures to accelerate Pb based on those parallelisms are discussed. Finally, time performance, accuracy and scalability of the parallel Pb detector accelerated by hardware are presented. After being implemented in a Xilinx Virtex-7 FPGA, XC7VX485T-2FFG1761C, the parallel Pb detector with the working frequency of 200 MHz takes 6.3 ms to process an 321×481321×481 image. It is more competitive than Pb implemented on CPUs when larger images are processed. This paper demonstrates a promising way to improve the real-time performance of high-quality image boundary detection systems, especially when embedded and real-time systems are taken into account.