A fitted finite element method for the numerical approximation of void electro-stress migration

Microelectronic circuits usually contain small voids or cracks, and if those defects are large enough to sever the line, they cause an open circuit. A fully practical finite element method for the temporal analysis of the migration of voids in the presence of surface diffusion, electric loading and elastic stress is presented. We simulate a bulk–interface coupled system, with a moving interface governed by a fourth-order geometric evolution equation and a bulk where the electric potential and the displacement field are computed. The method presented here follows a fitted approach, since the interface grid is part of the boundary of the bulk grid. A detailed analysis, in terms of experimental order of convergence (when the exact solution to the free boundary problem is known) and coupling operations (e.g., smoothing/remeshing of the grids, intersection between elements of the two grids), is carried out. A comparison with a previously introduced unfitted approach (where the two grids are totally independent) is also performed, along with several numerical simulations in order to test the accuracy of the methods.