Comparative study of system on chip based solution for floating and fixed point differential evolution algorithm

• We compared FPGA based scalable fixed and floating point DE IP cores for PSoC.
• Maximum frequency of float DE IP is 100–120 MHz and fixed DE IP is 30–60 MHz.
• Evaluated APU and SU accelerators for both arithmetic of DE IP on PPC440 based SoC.
• The proposed DE SoC system tested with different benchmark test functions.
• DE IP core is realized by solving IIR based system identification problem.

This paper presents performance study of scalable hardware accelerator for fixed and floating point differential evolution (DE) algorithms in field programmable gate array (FPGA) using programmable system on chip (PSoC) approach. The hardware intellectual property (IP) of the DE is interfaced as a Slave Unit (SU) as well as an Auxiliary Processor Unit (APU) with the PowerPC440 processor based System on Chip (SoC) platform on Xilinx Virtex-5 FPGA. Six numerical benchmark functions are optimized to validate the IP and its interface to processor. From the experimental results, it is observed that (i) Both SU and APU interfaces of fixed and float DE IPs have shown similar acceleration because of less communication overhead. (ii) Floating point DE has higher resource utilization compared to fixed point DE. (iii) Both interfaces of fixed and float DE SoC systems have shown similar power consumption. (iii) Finally as a case study, an Infinite Impulse Response (IIR) based system identification task with second and fourth order plant transfer functions is implemented on PSoC using the fixed and float DE IP cores with fabric co-processor bus (FCB) interface using APU controller. The experimental results reveal that the acceleration factor and resources utilization increases with the increase in problem complexity.