Giant Spin-Hall assisted STT-RAM and logic design

In recent years, Spin-Transfer Torque Random Access Memory (STT-RAM) has attracted significant attentions from both industry and academia due to its attractive attributes such as small cell area and non-volatility. However, long switching time and large programming energy of Magnetic Tunneling Junction (MTJ) continue being major challenges in STT-RAM designs. In order to overcome this problem, a Giant Spin-Hall Effect (GSHE) assisted STT-RAM structure (GSHE-RAM) has been recently invented. In this work, we investigate logic gates by using GSHE MTJs and two possible GSHE-RAM designs from the aspects of two different write access operations, namely, High Density GSHE-RAM and Disturbance Free GSHE-RAM, respectively. In High Density GSHE-RAM, GSHE current is shared by the entire bit line. Such a structure removes the GSHE control transistor from each GSHE-RAM cell and hence, substantially reduces the memory cell area. In Disturbance Free GSHE-RAM, one memory cell contains two transistors to remove the disturbance to the unselected bits and eliminate the possible erroneous flipping of the bits. In addition to memory designs, we also investigate logic gates by using GSHE MTJs. By leveraging the benefit of greater power efficiency and area density, GSHE MTJ elements become a suitable candidate for spintronic logic gates. Compare with traditional MOS transistors based logic gates, GSHE MTJ based logic can operate as a non-volatile memory and requires a much smaller number of elements to perform same logical operations (i.e., 'AND', 'OR', 'NAND' or 'NOR' gate.). And compare with other spin based logics, GSHE MTJ based logic also provides an better performance, excellent CMOS process compatibility and great fan-out ability.