کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
4970636 1450227 2017 11 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Secure split test techniques to prevent IC piracy for IoT devices
کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
Secure split test techniques to prevent IC piracy for IoT devices
چکیده انگلیسی
Globalization of semiconductor manufacturing and related activities has led to several security issues like counterfeiting, IP infringement and cloning etc. Counterfeiting not only affects the business and reputation of semiconductor vendor, it will affect the reliability of critical applications. Internet of Things (IoT's) is an emerging application area for semiconductors in which security is a prime concern. Identity or authentication of a device in the network of millions of devices in IoT's is very important. In this paper, we present Secure Split Test with functional testing capability (SSTF) scheme to mitigate the counterfeits coming out from untrusted foundries. The SSTF is suitable for low cost/low end devices. To address the identity management issue in IoT's and counterfeiting of ICs, a Physical Unclonable Function based SSTF (PUF-SSTF) is presented. PUF-SSTF is suitable for ICs targeted to use in smart phones and IoT 's. PUF-SSTF is a security solution to address: mitigating the counterfeit ICs coming out from untrusted foundries, identity management in IoT's and licensing the device features, which will benefit the fabless semiconductor vendors for licensing and entitlement management. The proposed SSTF and PUF-SSTF techniques are implemented in both ASIC and FPGA and security analysis is performed. The security analysis results are in par with earlier secure split test techniques like Connecticut Secure Split Test (CSST). The proposed techniques will create the comprehensive secure supply chain solution, which will benefit fabless semiconductor vendor and end-user.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 58, June 2017, Pages 390-400
نویسندگان
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