کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
4970691 | 1450226 | 2017 | 11 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning](/preview/png/4970691.png)
چکیده انگلیسی
Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits. In this paper, we a) provide a netlist-based circuit analysis technique to distinguish so-called critical configuration bits from essential bits in order to identify configuration bits which will need also state-restoring actions after a recovered SEU and which not. Furthermore, b) an alternative classification approach using fault injection is developed in order to compare both classification techniques. Moreover, c) we will propose a floorplanning approach for reducing the effective number of scrubbed frames and d), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits can be reduced by up to 48.5% in comparison to standard approaches.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 59, September 2017, Pages 98-108
Journal: Integration, the VLSI Journal - Volume 59, September 2017, Pages 98-108
نویسندگان
Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner,