A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40Â nm CMOS

Near-threshold operation is garnering growing attention for ultra-low power applications despite the fact the reliability of the near-threshold digital systems warrants unprecedented scrutiny of robustness measures to ensure correct functionality under stringent environmental and manufacturing scattering specifications. In this paper, an ideal theoretical read and write static noise margins (RSNM/WSNM) are discussed. In addition, a 12T SRAM bit cell is proposed in order to reach the theoretical WSNM limit. This could be achieved by eliminating a feedback of back-to-back inverters by means of data-dependent supply cutoff during write operation. This allows the proposed bit cell to enlarge write margin dramatically. Many previous works also attempt to cutoff the supply, but many of them were not data dependent. Monte-Carlo (MC) simulation results show the proposed 12T SRAM bit cell is more robust in static and dynamic noise margin than the conventional 6T and 8T SRAM bit cells as well as a 10T bit cell. The area overhead of the proposed bit cell is 1.96 times and 1.74 times greater than the 6T and 8T bit cells, respectively. Analytical models of WSNM for the 12T bit cell in the super-threshold region and the sub-threshold region are also proposed.