A 1.6 ps 7 b time to digital converter in 0.18 µm CMOS technology

A fine Time to Digital Converter (TDC) based on time difference amplification is proposed. A current difference based method is introduced to improve the limited input linear range of the conventional×2 Time Amplifier (TA). The modified TA is used in a proposed pipeline TDC to achieve a fine sub-gate delay resolution. A sign detection stage is implemented at the input of the TDC to avoid two separate circuits for conversion of positive and negative inputs, which decreases power consumption by roughly fifty percent. Furthermore, the delay cell circuits are modified to increase the TDC resolution and reduce its susceptibility to mismatch and process variations. The TDC resolution is 1.6 ps by post-layout simulation in 180nm CMOS technology. Power consumption of the introduced TDC at 50Msps and 1.2V supply voltage is 280uW.