A scalable decimation filter ASIC for high resolution digital magnetometer with sigma-delta modulator feedback loop

High-resolution digital magnetometers often use sigma-delta modulator feedback loops for large dynamic range, good linearity and low power consumption. A decimation filter is usually needed to obtain the high-resolution output data and reduce the output data rate at the same time. A scalable decimation filter application specific integrated circuit (ASIC) for high-resolution digital magnetometer with sigma-delta modulator feedback loop has been designed, implemented and fabricated. Keeping the decimation ratio of 128 to 1 fixed, the ASIC chip was carefully designed to be scaled with input data rate accordingly, thus maintaining the same resolution of 24 bits for the digital magnetometer. The ASIC chip consists of a cascaded integrator-comb (CIC) filter decimated by 16, a droop compensation programmable FIR1 filter decimated by 4, a brick-wall programmable FIR2 filter decimated by 2 and a 5th order sigma-delta bit stream generator for built-in-self-testing (BIST). The chip was designed and fabricated based on the GlobalFoundries 0.18 µm CMOS process. Its total die size is about 3×3 mm2, having 256,000 equivalent logic gates. In a typical working scenario with an input data rate of 128 kHz, the measured power consumption of the core powered with 1.8 V is about 0.9 mW.