کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
4971225 | 1450464 | 2017 | 7 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios](/preview/png/4971225.png)
چکیده انگلیسی
Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90Â ns consuming an average power of 1.2Â mW for an input reference frequency of 1.25Â GHz. It also operates over a wide lock range of 0.7-2.8Â GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 64, June 2017, Pages 92-98
Journal: Microelectronics Journal - Volume 64, June 2017, Pages 92-98
نویسندگان
Umakanta Nanda, Debiprasad Priyabrata Acharya,