Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios

Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90 ns consuming an average power of 1.2 mW for an input reference frequency of 1.25 GHz. It also operates over a wide lock range of 0.7-2.8 GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX.