A dynamic task mapping algorithm for SDNoC

The task mapping has a significant impact on the system performance of Network-on-Chip(NoC). In this paper, we propose a dynamic task mapping algorithm for Software-Defined-Network-on-Chip(SDNoC). The hierarchical design of SDNoC promotes the flexibility of NoC and provides the running environment for dynamic mapping algorithm with software techniques. The goal of dynamic task mapping is to minimize communication cost of the application execution and to achieve the load balance among routers. The tasks of applications are assigned to suitable network nodes by the proposed task coarse mapping and task fine mapping for minimum communication cost and flits load balance among routers. A simulation platform is presented to confirm the effectiveness of the proposed approach. The simulation results show that the communication cost and the standard deviation of routers flit load have been reduced by 2.8% and 8.1% compared with the reported dynamic mapping method. The execution time of applications and consuming time of mapping are less 9.3% and 28.2% compared with the reported dynamic mapping respectively.