A macro SPICE model for 2-bits/cell split-gate flash memory cell

A SPICE macro-model constructed of 3-series-connected-transistors is proposed to describe the IV behavior of a 2-bits/cell split-gate flash memory cell for the first time. The model features 3 different memory states of the cell, namely '11′, '10′ and '01′ at different temperatures (−40 to 125 °C). The cell is constructed of a select-gate transistor in the center with two symmetrical floating gate transistors in two sides. Using the method of capacitive coupling, the model describes the floating gate transistor with BSIM4 (level=54) model with the floating gate voltages changed into a linear combination of the control gate voltage and the select gate voltage. All the BSIM model parameter extraction strategies are applicable for the extraction flow. This novel 2-bits/cell split-gate flash memory cell is fabricated by a 90 nm 4-poly 4-metal CMOS process of Shanghai Huahong Grace Semiconductor Manufacturing Corporation.