A 12-bit 200MS/s pipeline ADC with 91Â mW power and 66Â dB SNDR

A 12-bit 200MS/s pipeline analog-to-digital converter (ADC) with sample-and-hold amplifier (SHA) is proposed in this paper. An innovative timing control technology is applied to the SHA in order to eliminate its nonlinear kickback, while the SHA eliminates bandwidth and timing mismatches between the input networks of the flash (sub-ADC) and of the multiplying DAC (MDAC) in the first stage, to improve the analog input bandwidth and to meet the requirements of a high-IF sampling ADC. A novel full complementary op-amp is utilized to reduce the overall power consumption of the ADC, which makes the power consumption of the SHA and of the first stage less than 20 mW. A new fully differential reference buffer and a clock receiver with duty-cycle stabilizer (DCS) are applied in the prototype ADC. The jitter of the clock receiver is less than 150 fs to avoid the SNR degradation. The ADC is implemented in 0.18 µm CMOS process and consumes 91 mW from a 1.8 V supply. The ADC achieves an SNDR of 66.10 dB and an SFDR of 84.45 dB with 10 MHz input signal, while maintaining an SNDR >65 dB and SFDR >80 dB up in the entire Nyquist band. Its input signal frequency is up to 500 MHz.