A cellular automata based self-correcting protocol processor for scalable CMPs

This work reports an effective design of protocol processor (PP), the key component of coherence controller, in a Chip Multiprocessors (CMPs) cache system. It caters to the need for determining the state of a data block in processors' private caches with high accuracy. An insignificant defect in the PP can introduce major inconsistencies in computing the states of cached copies of a data block. A realizable PP, therefore, is a necessity for accurate computation of cache line states. The proposed design is the outcome of radical change in the design approach of PP. The modeling tool of cellular automata (CA) is considered for the design. The special class of cellular automata with single length cycle attractors (SLCA) is tuned to replicate the PP for computing cache line states in CMPs. Theory has been developed to empower the SLCA based PP to sense its malfunctioning and that leads to the design of a self-correcting PP.