3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance

Domain wall memory (DMW) or Racetrack memory (RM) has attracted great attention for its enormous capacity. However, the array architecture are not clear. Prior arts have very low capacity utilization (only 50%) as well as high shift voltage. This paper proposed a 1 transistor X cells (1TXC) array architecture based on X-bar cell structure for 3D DWM, which realizes 100% capacity utilization, 50% shift power reduction and attains simplified peripheral decoding circuit as well as cost efficiency. Further, a corresponding anti-disturbance read operation algorithm is put forward, which can inhibit misread problem caused by sneaking current.