A novel time-interleaved two-step single-slope ADC architecture based on both resistor ladder and current source ramp generator

In this paper, analysis and design of the time-interleaved two-step single-slope ADCs are presented. In these types of ADCs, the ramp generator circuit is an obstacle for high-resolution specifications. A novel structure for enhancement of the ramp generator circuit, using both resistor ladder and current source ramp generator is proposed. By using the ramp generator and techniques such as time interleaving, device sharing, analog and digital supply separation, a fully differential low power ADC structure is presented. Besides, a calibration method is used for minimizing ADC output errors. Furthermore, the mathematical representation of the calibration process is expressed, and it is well matched with the simulation results. For more demonstration of the proposed structure, a 12-bit, 32 MS/s time-interleaved two-step single-slope ADC is designed and simulated in 0.18-μm CMOS, while it occupies an active area of 3 mm2. Simulation results show that the SNDR of the proposed ADC around Nyquist frequency is about 66.6 dB, while the total power consumption is about 1.9 mW, and the worst case figure of merit (FOM) and ENOB of the proposed ADC are 44.5 (fJ/conv.step) and 10.45-bit, respectively. In addition, the maximum INL of the proposed ADC before the calibration process is more than 43 LSB, while it decreases to 1.25 LSB after the calibration.