A fast correlated multiple sampling technique based on 12-bit SAR ADC with digital calibration for low-noise CMOS image sensor

A fast multiple correlated sampling technique based on successive approximation register analog-to-digital converter (SAR ADC) for low-noise CMOS image sensors is proposed in this paper. During the whole operation of the fast multiple correlated sampling, m-times samplings and conversions are achieved. The SAR ADC completes a full conversion in the first conversion and only converts lower M bits in the following conversions to decrease the total conversion time. The influences of three factors, the number of samplings, the number of bits converted in the repeated conversions and the resolution of ADC, on the fast multiple correlated sampling are analyzed in detail. A 12-bit SAR ADC with digital calibration based one bit redundancy to relieve the requirement of the capacitor mismatch is designed in the fast correlated multiple sampling technique. The proposed correlated multiple sampling technique is implemented and simulated through standard 180 nm CMOS process. The SAR ADC achieves 72.55 dB signal-to-noise-and-distortion ratio after digital calibration. The simulation results match the analysis well. Readout noise in CMOS image sensors can be reduced by the factor of m effectively with appropriate M based on the fast correlated multiple sampling technique. The total conversion time is decreased effectively, and it is only 10.9 μs for 16 times fast correlated multiple sampling. The fast multiple correlated sampling technique based on SAR ADC is suitable for low-noise and high-speed CMOS image sensor.