کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
4971332 | 1450470 | 2016 | 5 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Dynamic power reduction in digital pixel design for large format focal plane arrays
ترجمه فارسی عنوان
کاهش قدرت پویا در طراحی پیکسل دیجیتال برای آرایه های بزرگ کانال بزرگ
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
چکیده انگلیسی
This paper presents a design and analytical approach to significantly reduce the dynamic power consumption of front-end pixel design for digital readout integrated circuits (DROICs) in digital pixel sensor (DPS) arrays. DPS architecture relies on coarse quantization with pulse frequency modulation (PFM) and a novel approach of extended integration incorporated to achieve lower noise. The design is fabricated in 90 nm CMOS process with pixel pitch of 30 µm. Proposed architecture can attain eminently high charge handling capacity of 2.2Ge- with a quantization noise of 1072e- and extremely low power dissipation of 14.28 mW. The proposed dynamic power reduction paradigm enables to alleviate the overall power consumption to 35% as compared to state-of- art PFM based 256Ã256 DPS array with the lowest Figure of Merit (FoM) of 297fJ/LSB reported earlier. The power reduction escalates further for higher detector currents and large format Focal Plane Arrays (FPA). The proposed design is tested and compared to our previous DROIC measurement results and other works in terms of power and quantization noise.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 58, December 2016, Pages 9-13
Journal: Microelectronics Journal - Volume 58, December 2016, Pages 9-13
نویسندگان
Atia Shafique, Huseyin Kayahan, Sohaib Saadat Afridi, Omer Ceylan, Melik Yazici, Shahbaz Abbasi, Arman Galioglu, Yasar Gurbuz,