An automatic mode low-jitter pulsewidth control loop with broadband operation frequency

An automatic mode low-jitter pulsewidth control loop (PWCL) with enhanced operation frequency is presented in this paper. Using the automatic mode selector (AMS), the proposed PWCL can operate between pulsewidth modulating mode and tracking mode adaptively, avoiding extra power dissipation when a 50% duty cycle input clock is added. Based on the analysis of the delay time between the fixed falling edge and the rising edge generated by PWCL cycle, an auto delay time adjusting delay stage (ADTDS) is proposed to expand the locking frequency range of PWCL. Moreover, an improved charge pump and a novel delay stage are utilized to decrease the supply-induced jitter. The experimental results demonstrate that the proposed PWCL can lock the clock duty cycles for no more than 50±1% with 10-90% input duty cycle from 5 MHz to 750 MHz. At pulsewidth modulating mode, the measurement power dissipation and peak-to-peak jitter are 9.52 mW and 7.72 ps (rising edge) and 9.45 ps (falling edge), respectively, while at tracking mode, 0.6 mW and 10.1 ps achieved with an operating frequency of 750 MHz. The core area of chip is 220 µm×310 µm2.