High-speed low-power on-chip global interconnects using low-swing self-timed regenerators

In this paper, we present a mixed design of Low-Swing scheme and Self-Timed Regenerator (LS-STR). Our novel design reduces the energy-delay product (EDP) and eliminates one of the fabrication constraints resulting from multi-threshold transistors employed. Therefore, it is suitable for long global on-chip interconnects. We have simulated our design using CMOS 90-nm technology at 1.0 V power supply, to transmit signal along a 10-mm interconnect line. Our simulation results for different wire widths reveal that the propagation time delay is reduced by 39.1% for iso-power compared with that of the optimal repeater insertion case. Also, up to 23.2% power reduction is achieved for iso-delay mode. Moreover, we have compared our scheme against Self-Timed Regenerator (STR) scheme along all wire widths. Our results show power consumption and delay time reduction of 21.4% and 12.1% for iso-delay and iso-power modes, respectively. The time delay improvement is up to 15.1% in the best case. Furthermore, PVT variation simulation shows that the LS-STR has more tolerance to the parameter variations with respect to the STR design due to avoiding use of multi-threshold transistors in the LS-STR design. Moreover, we have analyzed the reliability of the circuit, considering process and power supply rail variations and inter-line crosstalk noise. The LS-STR improves the Signal to Noise Ratio (SNR) by 3.7% compared with the STR design. The key advantage of our LS-STR scheme is that there is no need for multiple-threshold process technology or an extra power supply rail.