On the design of combined LNA-VCO-mixer for low-power and low-voltage CMOS receiver front-ends

A low-power low-voltage CMOS receiver architecture with a combined LNA-VCO-mixer structure is proposed. An inversion-coefficient (IC) based design procedure is presented that facilitates finding a power-efficient operating point for the low-noise amplifier (LNA) and the voltage-controlled oscillator (VCO) blocks. At the architecture level, the bias currents of LNA and mixer are combined, filtered, and reused for the VCO. This approach facilitates lowering the supply voltage and improves the power efficiency of the system. As a proof of concept, a 2.4 GHz receiver suitable for wireless sensor network applications is designed and fabricated in a 0.13-µm CMOS process. The receiver has an intermediate frequency (IF) of 50 MHz. The RF-to-IF gain of the receiver is 30.1 dB and its noise figure (NF) is 8.3 dB. The combined LNA-VCO-mixer receiver consumes 510 µW from a 0.8-V supply.