کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
4971559 | 1450526 | 2017 | 8 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Improving the ESD self-protection capability of 60 V HV p-channel LDMOS large array device in 0.25 μm BCD process
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: Improving the ESD self-protection capability of 60 V HV p-channel LDMOS large array device in 0.25 μm BCD process Improving the ESD self-protection capability of 60 V HV p-channel LDMOS large array device in 0.25 μm BCD process](/preview/png/4971559.png)
چکیده انگلیسی
Large array devices (LAD) of MOSFETs are needed in most power ICs. NMOS transistors are used in current sinking while PMOS in current driving. Unlike the NMOS transistors, the high voltage PMOS transistors (HVPMOS) electrostatic discharge (ESD) self-protection of LAD for higher than 30 V applications are less extensively studied. In this paper, the device level improvements of the 60 V HVPMOS LAD of a 0.25 μm BCD process is studied to obtain good ESD protection margins. The effects of device and layout optimization guidelines are also examined. Furthermore, the developed approach is shown to be a low cost general solution for the HVPMOS LAD with poor ESD self-protection capability in a 0.25 μm BCD process.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Reliability - Volume 74, July 2017, Pages 110-117
Journal: Microelectronics Reliability - Volume 74, July 2017, Pages 110-117
نویسندگان
Hung-Wei Chen, Mi-Chang Chang,