Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools

This paper presents a novel low cost scheduling driven watermarking methodology for modern computer aided design (CAD) high level synthesis tools. The proposed watermarking algorithm is embedded in the scheduling module of a CAD high level synthesis (HLS) tool. The presented watermarking methodology is capable of reusable intellectual property (IP) core protection of control data flow graphs (CDFG) from a vendor's perspective based on user provided resource constraint and loop unrolling factor as inputs. The proposed low cost robust watermarking embedded inside high level synthesis process protects an IP core against threats such as false claim of ownership and piracy. The proposed watermarking satisfies desirable properties such as covertness, robustness, low embedding cost and low complexity. Results of comparison indicated significant reduction in embedding cost through proposed technique than similar state of the art techniques.