A SystemC Based Framework for Cycle Accurate Processor Simulation and Parameter Analysis

The development of new domain specific microprocessors architectures is a very complex task. Hardware designers are confronted with several hundred design parameters (e.g. cache size, ALU operation, etc.) which can be combined in a nearly arbitrary way to develop new architectures. Often these parameters are guessed by the designer or best practice is used to find an apparently good parameter set. The utilization of virtual hardware can be one solution to solve this problem. Different parameter sets can be evaluated inside a simulation environment, without the need for designing any real hardware. Unfortunately, most virtual hardware simulators are either to inflexible or not accurate enough to get valuable results. Therefore, this paper presents a SystemC based framework, which enables the construction of highly parameterizable virtual hardware processor models, directed at parameter analysis. The structure and working principle of two exemplary processors are showcasing the use of this framework. A presentation of how different parameter sets impact the programs execution time and power consumption of the processor will be given, as a result of the virtual hardwares execution.