Efficient routing techniques in heterogeneous 3D Networks-on-Chip

• Heterogeneous 3D NoCs have less vertical links by using both 2D and 3D routers.
• We propose adaptive routing techniques which balance the traffic in such NoCs.
• The routers architectures are implemented on 40 nm CMOS process technology.
• The routing algorithms are simulated with synthetic and realistic benchmarks.
• The adaptive router improves the performance up to 75% compared to the static one.

Three-dimensional Networks-on-Chips (3D NoCs) have recently been proposed to address the on-chip communication demands of future highly dense 3D multi-core systems. Homogeneous 3D NoC topologies have many Through Silicon Vias (TSVs) which have a costly and complex manufacturing process. Also, 3D routers use more memory and are more power hungry than conventional 2D routers. Alternatively, heterogeneous 3D NoCs combine both the area and performance benefits of 2D and 3D static router architectures by using a limited number of TSVs. To improve the performance of heterogeneous 3D NoCs, we propose an adaptive router architecture which balances the traffic in such NoCs. Particularly, experimental results show that our proposed architecture significantly improves the performance up to 75% by replacing 2D static routers with adaptive 2D routers in heterogeneous 3D NoCs, while keeping the maximum clock frequency, power and energy consumption of the adaptive router nearly at the same level as the static router.