Accurate hardware-based stereo vision

To enable both accurate and fast real-time stereo vision in embedded systems, we propose a novel stereo matching algorithm that is designed for high efficiency when realized in hardware. We evaluate its accuracy using the Middlebury Stereo Evaluation, revealing its high performance at minimum tolerance. To outline the resource efficiency of the algorithm, we present its realization as an Intellectual Property (IP) core that is designed for the deployment in Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs).

Research highlights
► Real-Time Stereo Vision using FPGAs.
► Gradient-based Census Transform combined with SAD allows for high accuracy.
► Sparse computation of the Hamming Distance reduces computational complexity.
► Highly parallel and pipelined hardware implementation.