Gate patterning in 14Â nm and beyond nodes: from planar devices to three dimensional Finfet devices

Schematic showing optimized gate patterning for (a) a slightly over-etched ONO mask profile on the α-Si dummy gate, (b) a top view of (a) showing a smooth sidewall, (c) α-Si dummy gate etch profile showing an almost perfectly steep shape and (d) a top view of (c) showing an uniform etch behavior.