کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
5367738 | 1388372 | 2008 | 5 صفحه PDF | دانلود رایگان |

This paper describes the advanced embedded silicon germanium (eSiGe) technologies to apply the 45 nm node CMOS fabrication technology. There are three key techniques as follows. The first technique is a low temperature of epitaxial growth at 550 °C to suppress staking faults in eSiGe layer. The second one is a controlling of recess shape for eSiGe. Sigma(Σ)-shaped recess is applied, because the strain force on the channel of MOSFET is increased effectively by narrowing spacing between source and drain. The third one is to apply particular surface cleaning treatment before the epitaxial growth, to get the excellent SiGe crystallinity. We demonstrated the drain current of Ion = 725 μA/μm and Ioff = 100 nA/μm for PMOSFET using above these techniques.
Journal: Applied Surface Science - Volume 254, Issue 19, 30 July 2008, Pages 6067-6071