Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications

• The usage of one’s complement instead of conventional two’s complement number system is explored. One’s complement provides a reduction in critical path and hardware complexity. A dynamic column shifting scheme for a pipelined multi-mode decoder is presented. The proposed scheme enables multi-mode operation with the minimal increase in the decoder area. A very low complexity local switch is presented to implement the proposed dynamic column shifting scheme.
• The proposed decoder occupies only 0.575 mm2 of core area using 65-nm CMOS technology. In addition, it achieves a throughput of 9.25 Gb/s at 400 MHz for all modes. In terms of throughput, hardware complexity, energy efficiency and area efficiency, the proposed multi-mode LDPC decoder is superior to the previous works.

This paper presents a novel multi-Gb/s multi-mode LDPC decoder architecture and efficient design techniques for gigabit wireless communications. An efficient dynamic and fixed column-shifting scheme is presented for multi-mode architectures. A novel low-complexity local switch is proposed to implement the dynamic and fixed column-shifting scheme. Furthermore, an efficient quantization method and the usage of a one׳s-complement scheme instead of a two׳s-complement scheme are explored. The proposed decoder achieves very high throughput with minimal area overhead. Post layout results using TSMC 65-nm CMOS technology shows much better throughput, as well as better area- and energy-efficiency, compared to other multi-mode LDPC decoders.