کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
538353 1450234 2015 9 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Memory customisations for image processing applications targeting MPSoCs
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
Memory customisations for image processing applications targeting MPSoCs
چکیده انگلیسی


• Instruction cache customisations increase MPSoC scalability.
• Data cache customisations through Pareto Analysis of custom cost function.
• Custom MPSoC multithreading for image processing applications.
• Performance increases up to 2.93×.
• Resource consumption reduction by up to 200%.

Multiprocessor System on Chips (MPSoCs) are quickly becoming the mainstay in embedded processing platforms due to their hardware and software design flexibility. This flexibility increases the design space for developers, introducing trade-offs between performance and resource/power consumption. This paper presents a comprehensive evaluation of memory customisations for MPSoCs. Custom arrangements of instruction and data cache are presented to optimise off-chip memory consumption and improve system performance. Off-chip memory management and threading are presented to balance the computational load on available processors and improve system performance. The proposed methods are applied to an object detection case study, where performance increases of up to 2.93x are achieved when compared to standard memory designs. Furthermore, the proposed techniques can increase the number of possible processors in an MPSoC by reducing the number of bus interconnects.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 51, September 2015, Pages 72–80
نویسندگان
, ,