An all-digital self-calibrated delay-line based temperature sensor for VLSI thermal sensing and management

• A self-calibration method for multiple delay-line based temperature sensors.
• The self-calibration removes sensitivities to process and voltage supply variations.
• The sensors were verified experimentally on 65 nm, 60 nm FPGAs, 65 nm and 0.13 µm ICs.
• One calibration block calibrates as many sensors, requiring additional NC registers.
• The runtime thermal profiles of the four microprocessor cores were obtained.

This paper presents a low power self-calibrated delay-line based temperature sensor intended for Very Large Scale Integration (VLSI) thermal management applications. It proposes a fully digital automatic self-calibration method that removes the sensitivity to process variations in delay-line based temperature sensors. This method requires only one calibration block to calibrate multiple delay-line based temperature sensors sequentially. Both the proposed temperature sensors and the self-calibration method were verified experimentally on field programmable gate arrays (FPGAs) and on 65 nm and 0.13 µm custom ICs. The measurement results on three 65 nm custom ICs show a resolution of 0.4 °C with 3σ errors of ±3.0 °C, from 20 to 80 °C. The proposed temperature sensors were implemented on a FPGA based VLSI thermal management system. Four microprocessor cores were mapped onto the corners of a Cyclone IV FPGA chip to emulate the VLSI load. Each core has a proposed temperature sensor close by. The runtime thermal profiles were obtained for four microprocessor cores, with eight different Dynamic Thermal Management (DTM) methods. Experimental results from different DTM techniques were studied.